(1) Field of the Invention
The present invention relates to microcomputers, methods of controlling cache memories, and methods of controlling clocks, and more particularly, to a microcomputer that controls a cache memory and a clock so as to increase the process speed, a method of controlling the cache memory, and a method of controlling the clock.
(2) Description of the Related Art
In recent years, a microcontroller has a built-in cache memory so as to reduce access to low-speed peripheral memories as much as possible, and thereby increase the process speed. In such a microcontroller, certain instructions are written in the program, so that the use of the cache memory can be controlled.
FIG. 13 is a block diagram showing the inner structure of a conventional microcontroller. A microcontroller 7 includes a CPU (Central Processing Unit) 70 that executes process routines, a cache memory 71 that stores a part of or all of a process routine which the CPU 70 frequently accesses, a cache control circuit 72 that determines whether the cache memory 71 can be used, and an interrupt controller 73 that determines an interrupt factor of the peripheral device from its priority level or masking state, and then transmits an interrupt request signal to the CPU 70. A ROM (Read Only Memory) 8 that stores process routines to be executed by the CPU 70 is connected to the microcontroller 7. The cache control circuit 72 includes a register 72a in which the usage status of the cache memory 71 is set.
FIG. 14 is a process transition chart of the CPU 70 of the conventional microcontroller 7. As shown in FIG. 14, the CPU 70 of the microcontroller 7 is to execute a main routine to perform a regular operation, and an interrupt routine corresponding to an interrupt factor 1. The main routine is executed through the cache memory 71, while the interrupt routine is executed without the cache memory 71.
When the interrupt factor 1 enters the interrupt controller 73, the interrupt controller 73 transmits an interrupt request signal to the CPU 70. Upon receipt of the interrupt request signal, the CPU 70 suspends the execution of the main routine, and starts executing the interrupt routine.
At this point, a cache-OFF instruction is written at the top of the program in which the interrupt routine has been written, so that the CPU 70 executes the interrupt routine without the cache memory 71. The CPU 70 executes the cache-OFF instruction, and stores the information that the cache memory 71 is not usable in the register 72a. In accordance with the information stored in the register 72a, the cache control circuit 72 prohibits the CPU 70 from using the cache memory 71. Thus, after the CPU 70 executes the cache-OFF instruction, the cache memory 71 is disabled.
When the execution of the interrupt routine is completed, a cache-ON instruction and a return instruction are written at the end of the program in which the interrupt routine has been written, so that the CPU 70 resumes the execution of the main routine using the cache memory 71. The CPU 70 executes the cache-ON instruction, and stores the information that the cache memory 71 is usable in the register 72a. In accordance with the information stored in the register 72a, the cache control circuit 72 cancels the prohibition on use of the cache memory 71. Thus, after the CPU 70 executes the cache-ON instruction, the cache memory 71 is enabled.
In the above conventional manner, the information for controlling the cache memory 71 needs to be stored in the register 72a after execution of a program. As a result, the cache-OFF instruction and the return instruction might be stored in the cache memory 71, as shown in FIG. 14. If so, the remaining capacity of the cache memory 71 becomes smaller, and a part of the main routine to be stored in the cache memory 71 might fail to be stored in the cache memory 71.
As described above, a part of the process routine to be stored in the cache memory and executed sometimes fail to be stored in the cache memory in the prior art. This results in a poor usage efficiency of the cache memory, and a decrease of the process speed.